ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 96
ST10F272B_12
Manufacturer Part Number
ST10F272B_12
Description
16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10F272B_12.pdf
(188 pages)
- Current page: 96 of 188
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System reset
20.4
96/188
Figure 23. Synchronous long hardware RESET (EA = 0)
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
3. 3 to 8 TCL depending on clock source selection.
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, e.g. to
leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous: there is no influence on Software Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to
Figure 27
5V operation), the asynchronous reset is then immediately entered.
by the internal filter (refer to
Figure 24
and
Figure 28
and
Figure 25
for bidirectional.
Section
Doc ID 11917 Rev 3
21.1).
for unidirectional SW reset timing, and to
ST10F272B/ST10F272E
Figure
26,
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