ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 178

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ST10F272B_12

Manufacturer Part Number
ST10F272B_12
Description
16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Electrical characteristics
24.8.19
178/188
External bus arbitration
V
Table 81.
1. Partially tested, guaranteed by design characterization.
Figure 58. External bus arbitration (releasing the bus)
1. The ST10F272 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
t
t
t
t
t
t
t
61
62
63
64
65
66
67
DD
Symbol
= 5V ± 10%, V
SR
CC
CC
CC
CC
CC
CC
External bus arbitration timings
HOLD input setup time
to CLKOUT
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
CSx release
CSx drive
Other signals release
Other signals drive
SS
Parameter
= 0V, T
1)
A
Doc ID 11917 Rev 3
= -40 to +125°C, C
1)
min.
18.5
– 4
– 4
F
TCL = 12.5 ns
CPU
64
.
= 40 MHz
L
= 50pF
max.
12.5
12.5
20
15
20
15
1/2 TCL = 1 to 64MHz
Variable CPU Clock
min.
18.5
– 4
– 4
ST10F272B/ST10F272E
max.
12.5
12.5
20
15
20
15
ns
ns
ns
ns
ns
ns
ns

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