ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 171

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272B/ST10F272E
Table 79.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
38
39
41
82
83
46
47
48
49
50
51
53
68
55
57
Symbol
CC
SR
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
SR
CC
CC
ALE falling edge to Latched
CS
Latched CS low to Valid Data
In
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
Demultiplexed bus timings (continued)
1. RW-delay and t
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3. Partially tested, guaranteed by design characterization.
Therefore address changes before the end of RD have no impact on read cycles.
Parameter
3
3
A
refer to the next following bus cycle.
– 8.5 + t
15.5 + t
14 + 2t
– 4 – t
2 + 2t
28 + t
10 + t
Doc ID 11917 Rev 3
2 + t
2 + t
min.
F
–
–
–
0
–
–
TCL = 12.5 ns
CPU
F
F
A
C
C
A
A
C
F
= 40 MHz
+ t
16.5 + t
16.5 + t
16.5 +
4 + t
6 – t
4 + t
max.
C
–
–
–
–
–
–
–
–
–
+ 2t
A
C
F
C
F
A
2TCL – 11 + 2t
TCL –10.5 + 2t
2TCL – 9.5 + t
3TCL – 9.5 + t
TCL – 10.5 + t
TCL – 10.5 + t
2TCL – 15 + t
– 8.5 + t
– 4 – t
min.
1/2 TCL = 1 to 64MHz
Variable CPU Clock
–
–
–
0
–
–
A
F
Electrical characteristics
C
C
C
F
F
A
A
2TCL – 8.5 + t
2TCL – 21 + t
3TCL – 21 + t
TCL – 8.5 + t
3TCL – 21 +
+ t
6 – t
max.
C
–
–
–
–
–
–
–
–
–
+ 2t
A
A
F
C
C
F
171/188
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns