ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 177
ST10F272B_12
Manufacturer Part Number
ST10F272B_12
Description
16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10F272B_12.pdf
(188 pages)
- Current page: 177 of 188
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ST10F272B/ST10F272E
Figure 57. CLKOUT and READY
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
7. The next external bus cycle may start here.
LOW at this sampling point terminates the currently running bus cycle.
WR).
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t
guaranteed, if READY is removed in response to the command (see Note 4).
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
Doc ID 11917 Rev 3
37
in order to be safely synchronized. This is
Electrical characteristics
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