ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 181

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272B/ST10F272E
24.8.20.2 Slave mode
Table 83.
t
t
t
t
t
t
t
t
t
310
311
312
313
314
315
316
317p
318p
Symbol
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR
SR
Figure 60. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable.
2. The bit timing is repeated for all bits to be transmitted or received.
V
SSC slave mode timings
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
DD
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
= 5V ±10%, V
Parameter
SS
(2)
= 0V, T
A
Doc ID 11917 Rev 3
= -40 to +125°C, C
(<SSCBR> = 0002h)
min.
150
@F
63
63
62
87
Max. Baudrate
–
–
–
0
6.6 MBd
CPU
= 40MHz
(1)
L
max.
150
)
10
10
55
= 50pF
–
–
–
–
–
t
t
4TCL + 12
6TCL + 12
310
310
Figure 60
(<SSCBR> = 0001h -
8TCL
min.
Variable Baudrate
/ 2 – 12
/ 2 – 12
–
–
–
0
Electrical characteristics
FFFFh)
uses the leading clock
262144 TCL
2TCL + 30
max.
10
10
–
–
–
–
–
181/188
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns