ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 182

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
Table 83.
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
2. Formula for SSC Clock Cycle time: t
182/188
t
t
317
318
Symbol
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only
with CPU clock lower than 32MHz (after checking that resulting timings are suitable for the master).
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
SR
SR
SSC slave mode timings (continued)
Figure 61. SSC slave timing
1. The phase and polarity of shift and latch edge of SCLK is programmable.
2. The bit timing is repeated for all bits to be transmitted or received.
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
Parameter
310
is 125ns (corresponding to 8Mbaud).
310
= 4 TCL * (<SSCBR> + 1)
Doc ID 11917 Rev 3
(<SSCBR> = 0002h)
min.
@F
31
Max. Baudrate
6
6.6 MBd
CPU
= 40MHz
(1)
max.
)
–
–
2TCL + 6
Figure 61
(<SSCBR> = 0001h -
min.
Variable Baudrate
6
ST10F272B/ST10F272E
FFFFh)
uses the leading clock
max.
–
–
Unit
ns
ns