ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 24

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Memory organization
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Memory organization
The memory space of the ST10F272 is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16M Bytes. The entire memory space can be accessed Byte wise or Word wise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFLASH: 256K Bytes of on-chip Flash memory. It is divided in 8 blocks (B0F0...B0F7) that
constitute the Bank 0. When Bootstrap mode is selected, the Test-Flash Block B0TF
(8Kbyte) appears at address 00’0000h: refer to
details on memory mapping in boot mode. The summary of address range for IFLASH is the
following:
Table 2.
IRAM: 2K Bytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 8K/16K+2K Bytes of on-chip extension RAM (single port XRAM) is provided as a
storage for data, user stack and code.
The XRAM is divided into 2 areas, the first 2K Bytes named XRAM1 and the second 8K/16K
Bytes named XRAM2, connected to the internal XBUS and are accessed like an external
memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (31.25ns
access at 64MHz CPU clock). Byte and Word accesses are allowed.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.
The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit
2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
Blocks
B0TF
Summary of IFLASH address range
B0F0
B0F1
B0F2
B0F3
B0F4
B0F5
B0F6
B0F7
Doc ID 11917 Rev 3
01’8000h - 01’FFFFh
02’0000h - 02’FFFFh
03’0000h - 03’FFFFh
04’0000h - 04’FFFFh
00’0000h - 00’1FFFh
00’2000h - 00’3FFFh
00’4000h - 00’5FFFh
00’6000h - 00’7FFFh
User Mode
Not visible
Section 5: Internal Flash memory
ST10F272B/ST10F272E
Size
32K
64K
64K
64K
8K
8K
8K
8K
8K
for more