ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 157

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272B/ST10F272E
Jitter at the PLL output can be due to the following reasons:
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Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.
Noise in the PLL loop
This contribution again can be caused by the following sources:
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Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the
loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is
practically independent on the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled
Oscillator). There are two main sources of noise: thermal (random noise, frequency
independent so practically white noise) and flicker (low frequency noise, 1/f). For the
frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f
region in the output noise spectrum, while the flicker noise in a 1/f
PLL input and supposing that the VCO is dominated by its 1/f
accumulated jitter is proportional to the square root of N, where N is the number of clock
periods within the considered time interval.
On the contrary, assuming again a noiseless PLL input and supposing that the VCO is
dominated by its 1/f
where N is the number of clock periods within the considered time interval.
The jitter in the PLL loop can be modelized as dominated by the i1/f
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 45
CPU frequencies) is reported: the curves represent the very worst case, computed taking
into account all corners of temperature, power supply and process variations: the real jitter
is always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds deterministic components to the PLL output jitter, independent on
multiplication factor. Its effects is strongly reduced thanks to particular care used in the
physical implementation and integration of the PLL module inside the device. Anyhow, the
sufficiently large to have the long term jitter. For N=1, this becomes the single period
jitter.
Jitter in the input clock
Noise in the PLL loop.
Device noise of the circuit in the PLL
Noise in supply and substrate.
the maximum jitter trend versus the number of clock periods N (for some typical
3
noise, the R.M.S. value of the accumulated jitter is proportional to N,
Doc ID 11917 Rev 3
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noise, the R.M.S. value of the
Electrical characteristics
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. Assuming a noiseless
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noise for N smaller
3
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noise
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