ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 155

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272B/ST10F272E
24.8.7
24.8.8
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
Phase Locked Loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
f
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
locked to f
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
keep it locked on f
one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is
negligible. Refer to next
Voltage Controlled Oscillator
The ST10F272 implements a PLL which combines different levels of frequency dividers with
a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In
detailed summary of the internal settings and VCO frequency is reported.
XTAL
x F). With every F’th transition of f
XTAL
. The slight variation causes a jitter of f
XTAL
. The relative deviation of TCL is the maximum when it is referred to
Section 24.8.9: PLL Jitter
Doc ID 11917 Rev 3
XTAL
the PLL circuit synchronizes the CPU clock to
for more details.
Table
CPU
69). The PLL multiplies the input
which also effects the duration of
CPU
is constantly adjusted so it is
Electrical characteristics
Table
70, a
CPU
CPU
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to
=