ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 97

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272B/ST10F272E
20.5
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it overflows and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to
Figure 27
Figure 24. SW / WDT unidirectional RESET (EA = 1)
Figure 24
and
Figure 28
and
Figure 25
for bidirectional.
Doc ID 11917 Rev 3
for unidirectional SW reset timing, and to
Figure
System reset
26,
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