HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 144

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

8.4
In external memory space, strobe signal is output based on the assumption of a directly connected
SRAM. The external memory space is allocated to the following areas:
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8.4.1
The bus cycle for external memory space access is 1 or 2 states. The number of states is controlled
with the wait states by the settings of wait state control registers 1–3 (WCR1–WCR3). For details,
see section 8.4.2., Wait State Control. Figures 8.11 and 8.12 illustrate the basic timing of external
memory space access.
128 HITACHI
Area 0 (when MD2–MD0 are 000 or 001)
Area 1 (when the DRAM enable bit (DRAME) of the BCR is 0)
Areas 2–4
Area 5 (space where address A27 is 1)
Area 6 (when the multiplexed I/O enable bit (IOE) bit of the BCR is 0, or space where address
A27 is 1)
Area 7 (space where address A27 is 0)
Figure 8.11 Basic Timing of External Memory Space Access (1-state read timing)
Accessing External Memory Space
Basic Timing
AD15–AD0
A21–A0
(Read)
(Read)
CSn
RD
CK
T1