HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 73

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

4.4.3
When an interrupt is generated, the INTC ascertains the interrupt rankings. NMI is always
accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the
interrupt mask bits (I3–I0) of the SR.
When an interrupt is accepted, interrupt exception processing begins. In the interrupt exception
processing sequence, the SR and PC are pushed onto the stack, and the priority level of the
accepted interrupt is copied to the interrupt mask level bits (I3–I0) in the SR. In NMI exception
processing, the priority ranking is 16 but the value 15 (H'F) is stored in I3–I0. The exception
service routine start address for the accepted interrupt is fetched from the exception vector table
and the program branches to that address and starts executing. For further information on
interrupts, see section 5.4, Interrupt Operation.
4.5
4.5.1
Table 4.8 shows the three types of instruction that start exception processing (trap instructions,
illegal slot instructions, and general illegal instructions).
Table 4.8
Type
Trap instruction
Illegal slot
instruction
General illegal
instructions
4.5.2
Trap instruction exception processing is carried out when a trap instruction (TRAPA) is executed.
The CPU then:
1. Saves the status register by pushing register contents onto the stack.
2. Pushes the program counter value onto the stack. The PC value saved is the top address of the
3. Reads an exception processing service routine start address from the vector table
next instruction after the TRAPA instruction.
corresponding to a vector number specified in the TRAPA instruction, branches to that
address, and starts program execution. The branch is not a delayed branch.
Interrupt Exception Processing
Instruction Exceptions
Types of Instruction Exceptions
Trap Instruction
Types of Instruction Exceptions
Source Instruction
TRAPA
Undefined code or instruction
that rewrites the PC located
immediately after a delayed
branch instruction (delay slot)
Undefined code in other than
delayed slot
Comments
—
Delayed branch instructions are: JMP, JSR,
BRA, BSR, RTS, RTE. Instructions that
rewrite the PC are: JMP, JSR, BRA, BSR,
RTS, RTE, BT, BF and TRAPA
—
HITACHI 55