HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 90

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HD6417021

Manufacturer Part Number
HD6417021
Description
SuperH RISC engine
Manufacturer
Hitachi Semiconductor
Datasheet
5.5
Table 5.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is
accepted.
Table 5.5
Item
Interrupt priority decision
and comparison with SR
mask bit
Wait for completion of
sequence currently being
executed by CPU
Time from interrupt
exception processing
(saving PC and SR and
fetching vector address)
until fetching of first
instruction of interrupt
service routine starts
Interrupt
response
Notes: m1–m4 are the number of states needed for the following memory accesses:
m1: SR save cycle (long word write)
m2: PC save cycle (long word write)
m3: Vector address read cycle (long word read)
m4: Fetch top instruction of interrupt service routine
Interrupt Response Time
Interrupt Response Time
Total
Minimum
Maximum
NMI or On-Chip
Interrupt
2
X ( 0)
5 + m1 + m2 + m3
7 + m1 + m2 + m3
10
11 + 2(m1 + m2 +
m3) + m4
Number of States
IRQ
3
8 + m1 + m2 + m3
11
12 + 2(m1 + m2 +
m3) + m4
Notes
The longest sequence is the
interrupt or address error
exception processing
sequence: X = 4 + m1 + m2
+ m3 + m4. If an interrupt-
masking instruction follows,
however, the time may be
longer.
0.50–0.55 s at 20 MHz
(m1 = m2 = m3 = m4) 0.90–
0.95 s at 20 MHz
HITACHI 73

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