HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 389

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Start
Parity
Stop
Parity
Stop
Start
1
1
Data
Data
bit
bit
bit
bit
bit
bit
Serial
Idle (mark
0
D
D
D
0/1
1
0
D
D
D
0/1
0
0
1
7
0
1
7
data
state)
TDRE
FER
RXI request
RXI interrupt handler
Framing error,
1 frame
reads data in RDR
ERI request
and clears RDRF to 0
Figure 13.8 Example of SCI Receive Operation (8-bit data with parity and one stop bit)
13.3.3
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.9 shows the example of communication among processors using the multiprocessor
format.
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