HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 200

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

source or destination. When RXI is set as the transfer request, however, the transfer source must
be the SCI’s receive data register (RDR). Likewise, when TXI is set as the transfer request, the
transfer source must be the SCI's transmit data register (TDR).
Table 9.4
RS3 RS2 RS1 RS0
0
0
0
0
1
1
1
1
SCI0, SCI1: Serial communications interface channels 0 and 1
ITU0–ITU3: Channels 0–3 of the 16-bit integrated-timer pulse unit.
RDR0, RDR1: Receive data registers 0, 1 of SCI
TDR0, TDR1: Transmit data registers 0, 1 of SCI
Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals. Note that transfer request signals from on-
chip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU
as well. When an on-chip peripheral module is specified as the transfer request source, set the
priority level values in the interrupt priority level registers (IPRC–IPRE) of the interrupt controller
(INTC) at or below the levels set in the I3–I0 bits of the CPU’s status register (SR) so that the
CPU does not acknowledge the interrupt request signal.
1
1
1
1
0
0
0
0
module (excluding DMAC)
0
0
1
1
0
0
1
1
Selecting On-Chip Peripheral Module Request Modes with the RS Bit
0
1
0
1
0
1
0
1
DMA
Transfer
Request
Source
SCI0
receiver
SCI0
trans-
mitter
SCI1
receiver
SCI1
trans-
mitter
ITU0
ITU1
ITU2
ITU3
DMA Transfer Request
Signal
RXI0 (SCI0 receive data full
interrupt transfer request)
TXI0 (SCI0 transmit data
empty interrupt transfer
request)
RXI1 (SCI1 receive data full
interrupt transfer request)
TXI1 (SCI1 transmit data
empty interrupt transfer
request)
IMIA0 (ITU0 input capture A/
compare-match A)
IMIA1 (ITU1 input capture A/
compare-match A)
IMIA2 (ITU2 input capture A/
compare-match A)
IMIA3 (ITU3 input capture A/
compare-match A)
Source
RDR0
Any
RDR1
Any*
Any*
Any*
Any*
Any*
Desti-
nation
Any*
TDR0
Any*
TDR1
Any*
Any*
Any*
Any*
HITACHI 185
Bus Mode
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Burst/Cycle
steal
Burst/Cycle
steal
Burst/Cycle
steal
Burst/Cycle
steal