HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 148

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

For CPU write cycles and DMAC dual mode write cycles to external memory space, the number
of states and wait state insertion cannot be controlled by WCR1. In areas 1, 3, 4, 5, and 7, the
WAIT signal is sampled and the number of states is 2 plus the number of wait states in the WAIT
signal (figure 8.13). In areas 0, 2 and 6, the number of states is 1 state plus the number of long
wait states plus the number of wait states in the WAIT signal (figure 8.14). Never write 0 in bits
7–2 and 0 of WCR1; only write 1. When area 1 is being used as external memory space, never
write 0 to bit 1 (WW1); always write 1.
132 HITACHI
Figure 8.14 Wait State Timing for External Memory Space Access (1 state plus long wait
Write
Read
WRH, WRL
AD15–AD0
AD15–AD0
state (when set to insert 3 states) plus wait states from WAIT signal)
A21–A0
WAIT
CSn
RD
CK
T1
T
set in WCR3
LW1
Wait states
T
LW2
signal input
from WAIT
Wait state
T
W
states set
in WCR3
T
Wait
LW3