HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 306

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

10.6.8
If an input capture signal is generated during the T3 state of a general register write cycle, the
input capture transfer takes priority and the write to the GR is not performed. The timing is shown
in figure 10.65.
10.6.9
When a counter is cleared by compare match, the counter is cleared in the last state in which the
TCNT value matches the GR value (when the TCNT is updated from the matching count to the
next count). The actual counter frequency is therefore given by the following formula:
292 HITACHI
Figure 10.65 Contention between General Register Write and Input Capture
f = /(N + 1)
(f: counter frequency. : operating frequency. N: value set in the GR.)
Contention between General Register Write and Input Capture
Note on Waveform Cycle Setting
Input capture
write signal
Address
Internal
TCNT
signal
GR
CK
T1
GR write cycle
GR address
T2
M
T3
M