HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 241

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

• Bit 1 (timer synchro 1 (SYNC1)): SYNC1 selects the synchronizing mode for channel 1.
Bit 1: SYNC1
0
1
• Bit 0 (timer synchro 0 (SYNC0)): SYNC0 selects the synchronizing mode for channel 0.
Bit 0: SYNC0
0
1
10.2.3
The timer mode register (TMDR) is an eight-bit read/write register that selects the PWM mode for
channels 0–4, sets the phase counting mode for channel 2, and sets the conditions for the overflow
flag (OVF). TMDR is initialized to H'80 or H'00 by a reset or the standby mode.
Note: Undefined
• Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
• Bit 6 (phase counting mode (MDF)): MDF selects the phase counting mode for channel 2.
Bit 6: MDF
0
1
Initial value:
Bit name:
Timer Mode Register (TMDR)
R/W:
Bit:
—
—
7
*
Description
The timer counter for channel 1 (TCNT1) operates independently
(Preset/clear of TCNT1 is independent of other channels) (initial value)
Channel 1 operates synchronously. Synchronized preset/clear of
TNCT1 enabled.
Description
The timer counter for channel 0 (TCNT0) operates independently
(Preset/clear of TCNT0 is independent of other channels) (initial value)
Channel 0 operates synchronously. Synchronized preset/clear of
TNCT0 enabled.
Description
Channel 2 operates normally (initial value)
Channel 2 operates in phase counting mode
MDF
R/W
6
0
FDIR
R/W
5
0
PWM4
R/W
4
0
PWM3
R/W
3
0
PWM2
R/W
2
0
PWM1
R/W
1
0
HITACHI 227
PWM0
R/W
0
0