HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 92

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

6.1
The user break controller (UBC) simplifies the debugging of user programs. Break conditions are
set in the UBC and a user break interrupt request is sent to the CPU in response to the contents of
a CPU or DMAC bus cycle. This function can implement an effective self-monitoring debugger,
enabling a program to be debugged by itself without using a large in-circuit emulator.
6.1.1
• The following break conditions can be set:
• When break conditions are met, a user break interrupt is generated. A user-created user break
• When a break is set to a CPU instruction fetch, the break occurs just before the fetched
6.1.2
Figure 6.1 is the block diagram of the user break controller.
interrupt exception routine can then be executed.
instruction.
Address
CPU cycle or DMA cycle
Instruction fetch or data access
Read or write
Operand size (long word access, word access, or byte access)
Overview
Features
Block Diagram
Section 6 User Break Controller (UBC)
HITACHI 75