HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 360

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

• Bit 3 (stop bit length (STOP)): STOP selects one or two bits as the stop bit length in the
Bit 3: STOP
0
1
• Bit 2 (multiprocessor mode (MP)): MP selects multiprocessor format. When multiprocessor
Bit 2: MP
0
1
• Bits 1 and 0 (clock select 1 and 0 (CKS1 and CKS0)): CKS1 and CKS0 select the internal
Bit 1: CKS1
0
1
asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the
clocked synchronous mode because no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of
the next incoming character.
format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored.
The MP bit setting is used only in the asynchronous mode; it is ignored in the clocked
synchronous mode. For the multiprocessor communication function, see section 13.3.3,
Multiprocessor Communication.
clock source of the on-chip baud rate generator. Four clock sources are available: , /4, /16,
and /64. For further information on the clock source, bit rate register settings, and baud rate,
see section 13.2.8, Bit Rate Register.
Bit 0: CKS0
0
1
0
1
Description
One stop bit. In transmitting, a single bit of 1 is added at the end of
each transmitted character (initial value).
Two stop bits. In transmitting, two bits of 1 are added at the end of
each transmitted character.
Description
Multiprocessor function disabled (initial value)
Multiprocessor format selected
Description
System clock ( ) (initial value)
/4
/16
/64
HITACHI 347