HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 192

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Bit 11:
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SCI0, SCI1: Serial communications interface channels 0 and 1.
ITU0–ITU3: Channels 0–3 of the 16-bit integrated-timer pulse unit.
Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be
2. Transfer from memory-mapped external device or external memory to external device
3. Transfer from external device with DACK to memory-mapped external device or
4. Dual address mode.
Bit 10:
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
selected in channels 2 and 3.
with DACK.
external memory.
Bit 9:
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 8:
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
DREQ (External request*
Reserved (illegal setting)
DREQ (External request*
DREQ (External request*
RXI0 (On-chip serial communication interface 0 receive data
full interrupt transfer request)*
TXI0 (On-chip serial communication interface 0 transmit data
empty interrupt transfer request)*
RXI1 (On-chip serial communication interface 1 receive data
full interrupt transfer request)*
TXI1 (On-chip serial communication interface 1 transmit data
empty interrupt transfer request)*
IMIA0 (On-chip ITU0 input capture/compare-match A
interrupt transfer request)*
IMIA1 (On-chip ITU1 input capture/compare-match A
interrupt transfer request)*
IMIA2 (On-chip ITU2 input capture/compare-match A
interrupt transfer request)*
IMIA3 (On-chip ITU3 input capture/compare-match A
interrupt transfer request)*
Auto-request (Transfer requests automatically generated
within DMAC)*
Reserved (illegal setting)
Reserved (illegal setting)
Reserved (illegal setting)
4
1
1
1
, dual address mode) (initial value)
, single address mode*
, single address mode*
4
4
4
4
4
4
4
4
HITACHI 177
2
3
)
)