HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 372

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HD6417021

Manufacturer Part Number
HD6417021
Description
SuperH RISC engine
Manufacturer
Hitachi Semiconductor
Datasheet
Table 13.4 Bit Rates and BRR Settings in Clocked Synchronous Mode
Bit Rate
110
250
500
1k
2.5k
5k
10k
25k
50k
100k
250k
500k
1M
2.5M
5M
Note
Blank: No setting available
—:
The BRR setting is calculated as follows:
B: bit rate (bit/s)
N: BRR setting for baud rate generator (0
n: baud rate generator clock source (n = 0, 1, 2, 3)
For the clock sources and values of n, see table 13.5.
:
(bits/s)
:
frequency (MHz)
Settings with an error of 1% or less are recommended.
Setting possible, but error occurs
Continuous transmit/receive not possible
Asynchronous mode
Clocked synchronous mode
n
3
2
1
1
0
0
0
0
0
0
0
0
2
N = [ /(64
N = [ /(8
N
70
124
249
124
199
99
49
19
9
4
1
0
n
2
2
1
1
0
0
0
0
0
0
0
0
2
2
2n – 1
2n – 1
4
N
249
124
249
99
199
99
39
19
9
3
1
0*
B)]
B)]
n
3
2
2
1
1
0
0
0
0
0
0
0
10
N
10
6
8
6
– 1
255)
N
124
249
124
199
99
199
79
39
19
7
3
1
– 1
(MHz)
n
1
1
0
0
0
0
0
0
0
10
N
249
124
249
99
49
24
9
4
0*
3
3
2
1
1
0
0
0
0
n
2
0
0
16
N
249
124
249
99
199
99
159
79
39
15
7
3
HITACHI 359
n
2
1
1
0
0
0
0
0
0
0
0
20
0*
N
124
249
124
199
99
49
19
9
4
1

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