HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 443

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

18.1.2
Table 18.2 summarizes the register related to the power-down state.
Table 18.2 Standby Control Register (SBYCR)
Name
Standby control register
18.2
The standby control register (SBYCR) is an 8-bit register that can be read or written to. It is set in
order to enter the standby mode and also sets the port states in standby mode. The SBYCR is
initialized to H'1F when reset.
•
SBY
0
1
•
HIZ
0
1
HITACHI 434
Bit 7 (standby (SBY)): SBY enables transition to the standby mode. The SBY bit cannot be set
to 1 while the timer enable bit (bit TME) in timer control/status register TCSR of watchdog
timer WDT is set to 1. To enter the standby mode, clear the TME bit to 0 to halt the WDT and
set the SBY bit.
Bit 6 (port high-impedance (HIZ)): HIZ selects whether I/O ports remain in their previous
states during standby, or are placed in the high-impedance state when the standby mode is
entered. The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the
I/O ports in high impedance, clear the TME bit to 0 before setting the HIZ bit.
Initial value:
Bit name:
Register
Standby Control Register (SBYCR)
R/W:
Bit:
Description
Executing SLEEP instruction puts the LSI into sleep mode (initial value)
Executing SLEEP instruction puts the LSI into standby mode
Description
Port states are maintained during standby (initial value)
Ports are placed in the high-impedance state in standby
SBY
R/W
7
0
Abbreviation
SBYCR
R/W
HIZ
6
0
—
—
5
0
R/W
R/W
—
—
4
1
Initial Value
H'1F
—
—
3
1
Address
H'5FFFFBC
—
—
2
1
—
—
1
1
Access size
8, 16, 32
—
—
0
1