HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 316

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Table 10.22 ITU Operating Modes (Channel 4) (cont)
Operating
Mode
Synch-
ronized
clear
Comple-
mentary
PWM
Reset
synchron-
ized PWM
Buffer
(BRA)
Buffer
(BRB)
Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and
302 HITACHI
: Settable, —: Setting does not affect current mode
2. When set for complementary PWM mode, do not simultaneously set channel 3 and
3. Counter clearing works with the reset-synchronized PWM mode, but TCNT4 runs
4. Clock selection when the complementary PWM mode is set should be the same for
5. In the reset-synchronized PWM mode, TCNT4 runs independently. The output
Sync
SYNC4
= 1
compare match B occur simultaneously, the compare match signal is inhibited.
channel 4 to function synchronously.
independently. The output waveform is not affected.
channels 3 and 4.
waveform is not affected.
TSNC
*
2
—
—
—
—
—
MDF FDIR PWM
—
—
—
—
—
TMDR
—
—
Counter Clear Function
Comp
PWM
CMD1
= 1,
CMD1
= 0
inhibit
ed
CMD1
= 1
CMD0
= 0
CMD1
= 1
CMD0
= 1
Reset
Sync
PWM
CMD1
= 1
CMD0
= 0
CMD1
= 1
CMD0
= 1
TFCR
Register Setting
*
3
Buf-
fer
BFA4
= 1,
others
free
BFB4
= 1,
others
free
Output
Level
Select IOA
—
—
—
TOCR
—
—
TIOR4
IOB
—
—
Clear
Select
CCLR1
= 1
CCLR0
= 1
CCLR1
= 0
CCLR0
= 0
*
5
TCR4
Clock
Select
*
*
4
5