HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 67

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

4.1.2
Exception sources are detected at the times indicated in table 4.1, whereupon processing starts.
Table 4.1
Exception Type
Reset
Address error
Interrupt
Instruction
When exception processing begins, the CPU operates as follows:
Resets: The initial values of the program counter (PC) and stack pointer (SP) are read from the
exception vector table (the respective PC and SP values are H'00000000 and H'00000004 for a
power-on reset and H'00000008 and H'0000000C for a manual reset). For more information on the
exception vector table, see section 4.1.3, Exception Vector Table. Next, the vector base register
(VBR) is cleared to zero and interrupt mask bits (I3–I0) in the status register (SR) are set to 1111.
Program execution starts from the PC address read from the exception vector table.
Address Errors, Interrupts and Instructions: SR and PC are pushed onto the stack indicated in
R15. For interrupts, the interrupt priority level is written in the interrupt mask bits (I3–I0). For
address errors and instructions, bits I3–I0 are not affected. Next, the start address is fetched from
the exception vector table, and program execution starts from this address.
4.1.3
Before exception processing can execute, the exception vector table must be set in memory. The
exception processing vector table holds the start addresses of exception service routines (the table
for reset exception processing stores initial PC and SP values). Different vector numbers and
vector table address offsets are assigned to different exception sources. The vector table addresses
are calculated from the corresponding vector numbers and vector address offsets. In exception
processing, the exception service routine start address is fetched from the exception vector table
indicated by this vector table address.
Exception Processing Operation
Exception Process Vector Table
Power-on
Manual
Trap instruction Starts when a trap instruction (TRAPA) is executed.
General illegal
instruction
Illegal slot
instruction
Exception Source Detection and Time of the Start of Processing
Source Detection and Time of the Start of Processing
Low-to-high transition at pin RES when NMI is high
Low-to-high transition at pin RES when NMI is low
Detected when instruction is decoded and starts after the
instruction that was executing prior to this point is completed.
Detected when instruction is decoded and starts after the
instruction that was executing prior to this point is completed.
Starts when undefined code is decoded at a position other than
directly after a delayed branch instruction (a delay slot).
Starts when undefined code or an instruction that rewrites the PC is
decoded directly after a delayed branch instruction (in a delay slot).
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