IC FLASH 8GBIT 48TSOP

 

MT29F8G08BAAWP:A TR

Manufacturer Part NumberMT29F8G08BAAWP:A TR
DescriptionIC FLASH 8GBIT 48TSOP
ManufacturerMicron Technology Inc
MT29F8G08BAAWP:A TR datasheet
 

Specifications of MT29F8G08BAAWP:A TR

Format - MemoryFLASHMemory TypeFLASH - Nand
Memory Size8G (1G x 8)InterfaceParallel
Voltage - Supply2.7 V ~ 3.6 VOperating Temperature0°C ~ 70°C
Package / Case48-TSOPLead Free Status / RoHS StatusLead free / RoHS Compliant
Speed-  
1
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NAND Flash Memory
MT29F4G08AAA, MT29F8G08BAA, MT29F8G08DAA, MT29F16G08FAA
Features
• Single-level cell (SLC) technology
• Organization
– Page size x8: 2,112 bytes (2,048 + 64 bytes)
– Block size: 64 pages (128K + 4K bytes)
– Plane size: 2,048 blocks
– Device size: 4Gb: 4,096 blocks; 8Gb: 8,192 blocks;
16Gb: 16,384 blocks
• READ performance
– Random READ: 25µs (MAX)
– Sequential READ: 25ns (MIN)
• WRITE performance
– PROGRAM PAGE: 220µs (TYP)
– BLOCK ERASE: 1.5ms (TYP)
• Data retention: 10 years
• Endurance: 100,000 PROGRAM/ERASE cycles
• First block (block address 00h) guaranteed to be
valid up to 1,000 PROGRAM/ERASE cycles
• Industry-standard basic NAND Flash command set
• Advanced command set:
– PROGRAM PAGE CACHE MODE
– PAGE READ CACHE MODE
– One-time programmable (OTP) commands
– Two-plane commands
– Interleaved die operations
– READ UNIQUE ID (contact factory)
– READ ID2 (contact factory)
• Operation status byte provides a software method of
detecting:
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: write protect entire device
• RESET required after power-up
• INTERNAL DATA MOVE operations supported
within the plane from which data is read
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__1.fm - Rev. B 2/07 EN
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Figure 1:
48-Pin TSOP Type 1
Options
2
• Density
1
– 4Gb (single die)
– 8Gb (dual-die stack 1 CE#)
– 8Gb (dual-die stack 2 CE#)
– 16Gb (quad-die stack)
• Device width: x8
• Configuration
# of die
1
2
2
4
• V
: 2.7–3.6V
CC
• Package
– 48 TSOP type I (lead-free plating)
– 48 TSOP type I OCPL
• Operating temperature
– Commercial (0°C to +70°C)
– Extended (–40°C to +85°C)
Notes: 1. For further details, see “Error Management”
on page 58.
2. For part numbering and markings, see
Figure 2 on page 2.
3. OCPL = off-center parting line.
4. For ET devices, contact factory.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
Features
# of CE#
# of R/B#
I/O
1
1
Common
1
1
Common
2
2
Common
2
2
Common
3
(lead-free plating)
4
©2006 Micron Technology, Inc. All rights reserved.

MT29F8G08BAAWP:A TR Summary of contents

  • Page 1

    ... INTERNAL DATA MOVE operations supported within the plane from which data is read PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__1.fm - Rev. B 2/07 EN Products and specifications discussed herein are subject to change by Micron without notice. 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Figure 1: 48-Pin TSOP Type 1 Options 2 • ...

  • Page 2

    ... Micron Parametric Part Search Web site at www.micron.com/products/parametric. If the device required is not on this list, contact the factory. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__1.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory ® NAND Flash devices are available in several different configurations and A A ...

  • Page 3

    ... Interleaved TWO-PLANE BLOCK ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 RESET FFh .56 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40aTOC.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...

  • Page 4

    ... Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 V Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 CC Timing Diagrams .65 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40aTOC.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...

  • Page 5

    ... ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Figure 55: INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40aLOF.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ©2006 Micron Technology, Inc. All rights reserved. List of Figures ...

  • Page 6

    ... Figure 77: 48-Pin TSOP OCPL Type 1 (WC Package Code .80 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40aLOF.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 6 ©2006 Micron Technology, Inc. All rights reserved. List of Figures ...

  • Page 7

    ... Table 18: AC Characteristics: Normal Operation .63 Table 19: PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40aLOT.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 ©2006 Micron Technology, Inc. All rights reserved. List of Tables ...

  • Page 8

    ... General Description NAND Flash technology provides a cost-effective solution for applications requiring high-density, solid-state storage. The MT29F4G08AAA is a 4Gb NAND Flash memory device. The MT29F8G08BAA is a two-die stack that operates as a single 8Gb device. The MT29F8G08DAA is a two-die stack that operates as two independent 4Gb devices. The MT29F16G08FAA is a four-die stack that operates as two independent 8Gb devices, providing a total storage capacity of 16Gb in a single, space-saving package ...

  • Page 9

    ... R/B# RE# CE# 1 CE2# NC Vcc Vss NC NC CLE ALE WE# WP Notes: 1. CE2# and R/B2# are available on 8Gb 2-CE# devices and 16Gb devices only. These pins are NC for other configurations. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Micron Technology, Inc ...

  • Page 10

    ... When these operations have completed, R/B# returns to the High-Z state. In the 8Gb configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb of memory enabled by CE2#. In the 16Gb configuration, R/B# is for the 8Gb of memory enabled by CE# ...

  • Page 11

    ... These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. This provides a memory device with a low pin count. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations ...

  • Page 12

    ... Bytes 2,112 through 4,095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 1 2 • • • • • • • • • • • • ...

  • Page 13

    ... Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address CA11 is “1,” then CA[10:6] must be “0.” PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 2,112 bytes 2,048 64 64 ...

  • Page 14

    ... CAx = column address; PAx = page address; BAx = block address CA11 is 1, then CA[10:6] must be “0.” 3. Die address boundary 0–4Gb 4Gb–8Gb. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Die 0 2,112 bytes 2,112 bytes 2,048 ...

  • Page 15

    ... NAND Flash memory will accept command, address, and data information. When the device is not performing an operation, the CE# pin is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption. See Figure 61 on page 69 and Figure 69 on page 75 for examples of CE# “ ...

  • Page 16

    ... Data is input on I/O[7:0]. See Figure 55 on page 66 for additional data input details. READs After a READ command is issued, data is transferred from the memory array to the data register on the rising edge of WE#. R/B# goes LOW for transfer is complete. When data is available in the data register clocked out of the part by RE# going LOW ...

  • Page 17

    ... Fall and t 2. Rise is primarily dependent on external pull-up resistor and external capacitive loading. t Fall ≈ 10ns at 3.3V See TC values in Figure 11 on page 18 for approximate Rp value and TC. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory ( ) V V MAX – ...

  • Page 18

    ... X H Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby. 2. Mode selection settings for this table Logic level HIGH Logic level LOW PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory I at 3.60V (MAX 2,000 4,000 6,000 ...

  • Page 19

    ... These commands are valid during busy when performing an interleaved die operation. See “Interleaved Die Operations” on page 47 for additional details. 6. The RANDOM DATA INPUT command is limited to use within a single page. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Number of Data Command Address ...

  • Page 20

    ... TWO-PLANE PAGE READ (00h-00h- 30h) command. 4. These commands are valid during busy when performing interleaved die operations. See “Interleaved Die Operations” on page 47 for additional details. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Number of Command Address Command Cycle 1 ...

  • Page 21

    ... RE# 00h I/Ox Address (5 cycles) PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t R), monitor the R/B# signal or, alternatively, issue a READ STATUS (70h) 30h Micron Technology, Inc., reserves the right to change products or specifications without notice. 21 Command Definitions ...

  • Page 22

    ... First, issue a normal PAGE READ (00h–30h) command sequence. See Figure 14 on page 23 for operation details. The R/B# signal goes LOW for transfer the first page of data from the memory to the data register. After R/B# returns to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the command register ...

  • Page 23

    Figure 14: PAGE READ CACHE MODE Operation CLE CE# WE# ALE t R R/B# RE# I/Ox 00h Address (5 cycles) 30h t DCBSYR1 t DCBSYR2 31h Data output (serial access) 31h Data output (serial access) t DCBSYR2 3Fh Data output ...

  • Page 24

    ... I/Ox Address, 1 cycle Notes: 1. See Table 8 on page 25 for byte definitions. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory REA t WHR Byte 0 Byte 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 24 ...

  • Page 25

    ... Notes binary hex. 2. The MT29F8G08DAA device ID code reflects the configuration of each 4Gb section. 3. The MT29F16G08FAA device ID code reflects the configuration of each 8Gb section. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 ...

  • Page 26

    ... Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6. See Figure 19 on page 29 and Figure 73 on page 77. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Page Read Page Read Cache Mode – ...

  • Page 27

    ... PAGE WRITE (10h) command. See Figure 18 on page 28 for the proper command sequence. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t CLR t REA 70h Status output Micron Technology, Inc ...

  • Page 28

    ... WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data register and R/B# returns to HIGH, memory array programming begins. When R/B# returns to HIGH, new data can be written to the cache register by issuing another CACHE PROGRAM command sequence ...

  • Page 29

    ... The written column addresses are ignored even though all 5 ADDRESS cycles are required. The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE command. Please refer to the description of this command in the following section. PROGRAM for INTERNAL DATA MOVE 85h-10h ...

  • Page 30

    ... RANDOM DATA INPUT command can be issued as many times as necessary before starting the programming sequence with 10h (see Figures 20 and 21). Because INTERNAL DATA MOVE operations do not use external memory, ECC cannot be used to check for errors before programming the data to a new page. This can lead to a data error if the source page contains a bit error due to charge loss or charge gain ...

  • Page 31

    ... One-Time Programmable (OTP) Area This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Ten full pages (2,112 bytes per page) of OTP data is available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area in any way they desire ...

  • Page 32

    ... When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 9 on page 26 possible to program each OTP page a maximum of four times. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Command Definitions Micron Technology, Inc., reserves the right to change products or specifications without notice PROG). The READ © ...

  • Page 33

    ... Col Col I/Ox A0h add 1 add 2 OTP DATA INPUT command R/B# Notes: 1. The OTP page must be within the 02h–0Bh range. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory OTP 00h 00h page bytes serial input x8 device 2,112 bytes Micron Technology, Inc ...

  • Page 34

    ... ADDRESS cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Finally, issue the 30h command. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Col 01h 00h 00h ...

  • Page 35

    ... CE#, must be identical for each plane. • The page address bits, PA[5:0], must be identical for both addresses. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t R) while the data is moved from the OTP page to the data register. The Col ...

  • Page 36

    ... RANDOM DATA READ (05h-E0h) command instead (see “RANDOM DATA READ 05h-E0h” on page 22). PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Command Definitions t R. During these transfers, R/B# goes LOW. When the trans- Micron Technology, Inc ...

  • Page 37

    Figure 26: TWO-PLANE PAGE READ Operation CLE WE# ALE RE# Page address M Col Col Row 00h I/Ox add 1 add 2 add 1 Column address J Plane 0 address R/B# CLE WE# ALE RE# I/ ...

  • Page 38

    Figure 27: TWO-PLANE PAGE READ Operation with RANDOM DATA READ R/B# RE# 00h Address (5 cycles) 00h Address (5 cycles) I/Ox Plane 0 address Plane 1 address R/B# RE# I/Ox 06h Address (5 cycles) E0h Plane 1 address 1 t ...

  • Page 39

    ... R/B# I/Ox 80h Address (5 cycles) Data 1st plane address PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory DBSY, write the 80h (or 81h) command to the command register; write DBSY input 11h 80h Address (5 cycles) 2nd plane address ...

  • Page 40

    ... WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data registers and R/B# returns HIGH, memory array programming to both planes begins. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2 ...

  • Page 41

    ... For details on this command, see “RANDOM DATA INPUT 85h” on page 27. See Figure 29 on page 40 for an example. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Command Definitions t CBSY) is determined by the actual program- Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 42

    ... Finally, write 35h to the command register. After the 35h command, R/B# goes LOW for their respective cache registers. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t DBSY 11h 80h Address/data input ...

  • Page 43

    ... The memory device is now ready to accept the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-80h-10h) command. TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-80h-10h After the TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command has been issued and R/B# goes HIGH (or the status register bit 6 is “1”), the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-80h-10h) command is used ...

  • Page 44

    ... Address (5 cycles) I/Ox 1st-plane source t DBSY R/B# 80h I/Ox Address (5 cycles) (or 81h) 2nd-plane destination 1 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t R Address (5 cycles) 35h 2nd-plane source t PROG 10h 70h Status t R 35h 85h Address (5 cycles) ...

  • Page 45

    ... RE# I/Ox 60h Address input (3 cycles) 1st plane PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t BERS are READ STATUS (70h), TWO-PLANE/MULTIPLE-DIE READ STATUS 60h Address input (3 cycles) D0h 2nd plane Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 46

    ... Figure 34: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle CE# CLE WE# ALE RE# I/Ox PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 78h Address (3 cycles) Micron Technology, Inc., reserves the right to change products or specifications without notice. 46 Command Definitions WHR t REA Status output ...

  • Page 47

    ... I/Ox 80h Address Data 10h Die 1 R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external) PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 80h Address Data 10h Die 2 47 Command Definitions 80h Address Data 10h 80h Address ...

  • Page 48

    ... I/Ox 80h Address Data 15h Die 1 R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external) PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 80h Address Data 10h 78h Die 2 80h Address Data 15h Die 2 48 Command Definitions ...

  • Page 49

    ... The interleaved TWO-PLANE PROGRAM PAGE operation must meet two-plane addressing requirements. See “Two-Plane Addressing” on page 35 for details. RANDOM DATA INPUT (85h) is permitted during interleaved TWO-PLANE PROGRAM PAGE operations. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 80h Address Data 15h 78h ...

  • Page 50

    ... R/B# (die 2 internal) R/B# (external) 1 Notes: 1. Two-plane addressing requirements apply. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 80h Address Data 10h 80h Die 1 80h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 51

    Figure 40: Interleaved TWO-PLANE PROGRAM PAGE Operation with Status Register Monitoring 80h 11h I/Ox Address Data Die 1 R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external) 80h I/Ox 78h Address Status Die 1 R/B# (die 1 internal) R/B# ...

  • Page 52

    ... R/B# (die 2 internal) R/B# (external) I/Ox R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external) 1 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 80h Address Data 15h 80h (or 81h) Die 1 80h Address Die 1 52 Command Definitions Address ...

  • Page 53

    Figure 42: Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operation with Status Register Monitoring 80h Address Data 11h I/Ox Die 1 R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external) I/Ox 78h 80h Address Status Die 1 R/B# (die 1 ...

  • Page 54

    ... The interleaved TWO-PLANE BLOCK ERASE operation must meet two-plane addressing requirements. See “Two-Plane Addressing” on page 35 for details. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory D0h Address Die 2 60h ...

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    Figure 45: Interleaved TWO-PLANE BLOCK ERASE Operation with R/B# Monitoring I/Ox 60h Address 60h Address D0h Die 1 Die 1 R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external) Notes: 1. Two-plane addressing requirements apply. Figure 46: Interleaved TWO-PLANE ...

  • Page 56

    ... RESET Operation RESET FFh The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid ...

  • Page 57

    ... WE# I/Ox WP# R/B# Figure 50: PROGRAM Enable WE# I/Ox WP# R/B# PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t WW 60h D0h t WW 60h D0h t WW 80h 10h Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 Command Definitions ...

  • Page 58

    ... Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: • ...

  • Page 59

    ... CC Storage temperature Short circuit output current, I/Os Table 12: Recommended Operating Conditions Parameter/Condition Operating temperature V supply voltage CC Ground supply voltage PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory SS Symbol MT29FxG08xAA V IN MT29FxG08xAA STG Symbol T Commercial ...

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    ... Figure 52: AC Waveforms During Power Transitions CLE V CC WP# WE# I/Ox R/B# PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory is internally monitored. When device: ≈ 2.5V HIGH 10µs FFh 60 Electrical Characteristics goes below approximately 2.0V, CC during power cycling ...

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    ... Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid up to 1,000 PROGRAM/ERASE cycles. 3. Each 4Gb section has a maximum of 80 invalid blocks. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Conditions 25ns; CE ...

  • Page 62

    ... For PAGE READ CACHE MODE and PROGRAM PAGE CACHE MODE operations, cache mode timing applies. 2. Timing for the first rising edge of WE# for data input. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Symbol Device C MT29F4G08AAA IN ...

  • Page 63

    ... The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. Thereafter, the device goes busy for maximum 5µ not issue a new command during PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Cache Mode Symbol Min Max ...

  • Page 64

    ... LPROG = address load time (last page) - data load time (last page). 4. Typical PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t t PROG (last page) + PROG (last - 1 page) - command load time (last page PROG time may increase for two-plane operations. ...

  • Page 65

    ... Timing Diagrams Figure 53: COMMAND LATCH Cycle CLE CE# WE# ALE I/Ox Figure 54: ADDRESS LATCH Cycle CLE CE# WE# ALE I/Ox PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t CLS t CLH ALS t ALH COMMAND t CLS ALS t ALH Col Col ...

  • Page 66

    ... ALS ALE WE# I/Ox Notes Figure 56: SERIAL ACCESS Cycle After READ t CEA CE# t REA t RP RE# I/ R/B# Note: Use this timing diagram for PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Final = 2,111 (x8). t REA t REH t RHZ D D ...

  • Page 67

    ... RE# t CEA I/ R/B# Note: Use this timing diagram for Figure 58: READ STATUS Operation CLE CE# WE# RE# I/Ox PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory REH t REA t REA t RLOH D D OUT OUT t RC < 30ns. t CLR t CLH t CLS ...

  • Page 68

    ... Figure 60: PAGE READ Operation CLE CE WE# ALE RE# Col I/Ox 00h add 1 R/B# PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory ALH t ALS Row add 1 Row add 2 Row add Col Row Row Row add 2 add 1 add 2 ...

  • Page 69

    ... RANDOM DATA READ Operation CLE CE# WE# ALE RE# Col Col Row I/Ox 00h add 1 add 2 add 1 Column address N R/B# PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t R 30h t CEA CE# t REA t CHZ t COH RE# Out I/ Row Row ...

  • Page 70

    Figure 63: PAGE READ CACHE MODE Operation, Part CLE t CLS t CLH CE WE# ALE RE Col Col Row Row I/Ox 00h add 1 add 2 ...

  • Page 71

    Figure 64: PAGE READ CACHE MODE Operation, Part CLE t CLS t CLH CE# WE# t CEA ALE REA D D ...

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    Figure 65: PAGE READ CACHE MODE Operation without R/B#, Part CLE t t CLS CLH CE WE# ALE RE Col Col Row Row Row I/Ox 00h add ...

  • Page 73

    Figure 66: PAGE READ CACHE MODE Operation without R/B#, Part CLE t CLS t CLH CE# WE# t CEA ALE REA D D I/Ox OUT ...

  • Page 74

    ... PROGRAM PAGE Operation CLE CE WE# ALE RE# Col Col I/Ox 80h add 1 add 2 SERIAL DATA INPUT command R/B# PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory WHR t REA Byte 0 Byte 1 t ADL Row Row Row add 1 add 2 add 3 N ...

  • Page 75

    ... WE# ALE RE# Col Col Row Row I/Ox 80h add 1 add 2 add 1 add 2 SERIAL DATA INPUT command R/B# PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Data input CE WE# t ADL Row D D Col IN IN 85h add 3 N N+1 ...

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    ... Row Row I/Ox 80h add 1 add 2 add 1 add 2 add 3 SERIAL DATA INPUT R/B# Last page - 1 PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory Row Col Col Row 35h 85h add 3 add 1 add 2 add 1 Busy INTERNAL DATA MOVE ...

  • Page 77

    Figure 73: PROGRAM PAGE CACHE MODE Operation Ending on 15h CLE CE ADL WE# ALE RE# Col Col Row Row Row D I/Ox IN 80h add 1 add 2 add 3 add 1 add 2 N SERIAL ...

  • Page 78

    ... AUTO BLOCK ERASE SETUP command Figure 75: RESET Operation CLE CE# WE# R/B# I/Ox FFh RESET command PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory BERS Row D0h add 3 ERASE command Busy RST 78 Timing Diagrams t WHR Status 70h ...

  • Page 79

    ... Note: All dimensions are in millimeters. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 20.00 ±0.25 18.40 ±0.08 See detail A 1.20 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. 79 Package Dimensions ...

  • Page 80

    ... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory 20.00 ±0.25 18.40 ±0.08 See detail A 1.20 MAX ® ...

  • Page 81

    ... Table 19 on page 64: Changed Rev 8/06 • Initial release. PDF: 09005aef81b80e13/Source: 09005aef81b80eac 4gb_nand_m40a__2.fm - Rev. B 2/07 EN 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory t t CBSY (MAX) and PROG (MAX) to 600µs. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...