MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 41

• Manufacturer Part Number: MT29F8G08BAAWP:A TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08BAAWP:A TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
When R/B# returns HIGH, new data can be written to the cache registers by issuing
another TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h) command
sequence. The time that R/B# stays LOW (
ming time of the previous operation. For the first cache operation, the duration of
is the time it takes for the data to be copied from the cache registers to the data registers.
On the second and subsequent TWO-PLANE PROGRAM PAGE CACHE MODE opera-
tions, transfer from the cache registers to the data registers is delayed until the current
data register contents have been programmed into the arrays.
If the R/B# pin is used to determine programming completion, the last operation of the
program sequence must use the TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h)
command instead of the TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-
15h) command. If the TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h)
command is used for the last operation, then use READ STATUS (70h) to monitor opera-
tion progress; status register bit 5 indicates when programming is complete. See Table 9
on page 26 for details of the status register.
To determine when the current TWO-PLANE PROGRAM PAGE CACHE MODE (80h-
11h-80h-10h) operation has completed, issue the READ STATUS (70h) command and
check status register bits 5 and 6. When the device is ready, use status register bit 0 to
determine if the current operation passed and status register bit 1 to determine if the
previous operation passed. If either bit 0 or bit 1 = 1, indicating a failed operation, then
use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twice—once for
each plane—to determine which current or previous plane operation failed. For more
information on status register bit definitions, see Table 9 on page 26.
During the serial data input for either plane, the RANDOM DATA INPUT (85h)
command can be used any number of times to change the column address within that
plane. For details on this command, see “RANDOM DATA INPUT 85h” on page 27. See
Figure 29 on page 40 for an example.
41
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CBSY) is determined by the actual program-
Command Definitions
©2006 Micron Technology, Inc. All rights reserved.
t
CBSY