W9751G6IB-25 Winbond Electronics, W9751G6IB-25 Datasheet - Page 22

• Manufacturer Part Number: W9751G6IB-25
• Description: IC DDR2-800 SDRAM 512MB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W9751G6IB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.8
(CKE = "H", CS = "H" or CKE = "H", CS = "L", RAS = "H", CAS = "H", WE = "H", BA0, BA1,
A0 to A12 = Don’t Care)
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be
stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least t
must be satisfied before a valid command can be issued to the device to allow for any internal refresh
in progress. CKE must remain HIGH for the entire Self Refresh exit period t
except for self refresh re-entry.
Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting
at least t
commands must be registered on each positive clock edge during the Self Refresh exit interval t
ODT should be turned off during t
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2
SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh
mode.
7.3.9
( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don’t Care)
Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles
at an average periodic interval of
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle)
state. A delay between the auto refresh command (REF) and the next activate command or
subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (t
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command
and the next Refresh command is 9 x t
CLK/CLK
CKE
CMD
Self Refresh Exit Command
Refresh Command
XSNR
Precharge
T0
"HIGH"
period and issuing one refresh command (refresh period of t
T1
NOP
≧ tRP
T2
NOP
t
XSRD
REFI (max.)
Figure 13—Refresh command
.
REFI
T3
.
REF
.
≧ tRFC
- 22 -
Tm
REF
Publication Release Date: Oct. 23, 2009
XSRD
≧ tRFC
RFC
W9751G6IB
Tn
). NOP or Deselect
for proper operation
NOP
Tn + 1
Revision A06
ANY
XSNR
RFC
XSNR
).
.