W9751G6IB-25 Winbond Electronics, W9751G6IB-25 Datasheet - Page 48

• Manufacturer Part Number: W9751G6IB-25
• Description: IC DDR2-800 SDRAM 512MB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W9751G6IB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. There are two sets of values listed for Command/Address input hold time: tIH(base) and tIH(ref). The tIH(ref) value (for
12. The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as
14. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is
15. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a
16. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and
17. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and
tRPST end point
reference only) is equivalent to the baseline value of tIH(base) at VREF when the slew rate is 1.0 V/nS. The baseline value
tIH(base) is the JEDEC defined value, referenced from the input signal crossing at the VIL(dc) level for a rising signal and
VIH(dc) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to
1.0 V/nS, then the baseline values must be derated by adding the values from table tIS/tIH derating values for DDR2-667,
DDR2-800 (page 55).
parameter, but system performance (bus turnaround) will degrades accordingly.
well as output Slew Rate mismatch between DQS / DQS and associated DQ in any given cycle.
no longer driving (tRPST), or begins driving (tRPRE). Figure 18 shows a method to calculate these points when the device
is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage
measurement points are not critical as long as the calculation is consistent.
specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Figure 18
shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the
signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is
consistent. tLZ(DQ
treated as single-ended signal.
DM input setup time: tDS(base) and tDS(ref). The tDS(ref) value (for reference only) is equivalent to the baseline value
tDS(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDS(base) is the JEDEC defined value,
referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and
from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the
device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the
differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from
table of DDR2-667, DDR2-800 tDS/tDH derating with differential data strobe (page 60).
DM input hold time: tDH(base) and tDH(ref). The tDH(ref) value (for reference only) is equivalent to the baseline value
tDH(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDH(base) is the JEDEC defined value,
referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and
from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the
device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the
differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from
table of DDR2-667, DDR2-800 tDS/tDH derating with differential data strobe (page 60).
tHZ,tRPST end point = 2 x T1 - T2
Figure 18 — Method for calculating transitions and endpoints
tHZ
T1 T2
)
refers to tLZ of the DQ’s and tLZ(DQS) refers to tLZ of the (UDQS, LDQS, UDQS and LDQS ) each
VOH - x mV
VOH - 2x mV
VOL + 2x mV
VOL + x mV
VTT + 2x mV
VTT - 2x mV
VTT + x mV
VTT - x mV
tLZ,tRPRE begin point = 2 x T1 - T2
- 48 -
T1 T2
Publication Release Date: Oct. 23, 2009
tLZ
tRPRE begin point
W9751G6IB
Revision A06