MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 106

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGM)
8.6.2 PLL Bandwidth Control Register (PBWC)
Data Sheet
106
NOTE:
PLLON — PLL On Bit
BCS — Base Clock Select Bit
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register.
The PLL bandwidth control register does the following:
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, DCLK1 (BCS = 1). Reset sets this bit so that the loop can
stabilize as the MCU is powering up.
This read/write bit selects either the crystal oscillator output,
OSCXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, DCLK1. BCS cannot be set while the PLLON bit is clear. After
toggling BCS, it may take up to three OSCXCLK and three CGMVCLK
cycles to complete the transition from one source clock to the other.
During the transition, DCLK1 is held in stasis. Reset and the STOP
instruction clear the BCS bit.
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•
•
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1 = PLL on
0 = PLL off
1 = DCLK1 driven by CGMVCLK
0 = DCLK1 driven by OSCXCLK
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode
Clock Generator Module (CGM)
MC68HC908LD64
Freescale Semiconductor
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Rev. 3.0