MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 33

IC MCU 8BIT FOR LCD 64-QFP

MC908LD64IFUE

Manufacturer Part Number
MC908LD64IFUE
Description
IC MCU 8BIT FOR LCD 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LD64IFUE

Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
I²C, USB
Peripherals
OSD, POR, PWM
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LD
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, USB
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LD64IFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908LD64IFUE
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC908LD64IFUE
Quantity:
17
MC68HC908LD64
Freescale Semiconductor
Rev. 3.0
1. DDC is a VESA bus standard.
2. IIC is a proprietary Philips interface bus.
Full Universal Serial Bus (USB) specification 1.1, composite hub
with embedded functions, including:
– One 12MHz upstream port
– Four 12MHz/1.5MHz downstream ports
– One hub control endpoint with 8-byte transmit buffer and
– One hub interrupt endpoint with 1-byte transmit buffer
– One device control endpoint with 8-byte transmit buffer and
– Two device interrupt endpoints with shared 8-byte transmit
DDC12AB
– DDC1 hardware
– Multi-master IIC
Additional multi-master IIC module
In-system programming capability using USB or DDC12AB
communication, or standard serial link on PTA0 pin
System protection features:
– Optional computer operating properly (COP) reset
– Illegal opcode detection with reset
– Illegal address detection with reset
Master reset pin (with internal pull-up) and power-on reset
IRQ interrupt pin with internal pull-up and schmitt-trigger input
64-pin quad flat pack (QFP) package
8-byte receive buffer
8-byte receive buffer
buffer
General Description
1
module with the following:
2
hardware for DDC2AB; with dual address
General Description
Data Sheet
Features
33

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