MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 124

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
9.6.1 Interrupts
Data Sheet
124
INTERRUPT
I BIT
R/W
INTERRUPT
IDB
I BIT
IAB
R/W
IDB
IAB
MODULE
MODULE
DUMMY
DUMMY
SP – 4
SP
An interrupt temporarily changes the sequence of program execution to
respond to a particular event.
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
9-9
PC – 1[7:0] PC – 1[15:8]
CCR
shows interrupt recovery timing.
SP – 1
SP – 3
Figure 9-9. Interrupt Recovery
Figure 9-8
System Integration Module (SIM)
A
SP – 2
SP – 2
X
X
.
Interrupt Entry
SP – 3
SP – 1
Figure 9-8
PC – 1[15:8] PC – 1[7:0]
A
Figure 9-10
SP – 4
SP
CCR
shows interrupt entry timing.
VECT H
PC
OPCODE
V DATA H
flow charts the handling of
VECT L
PC + 1
MC68HC908LD64
OPERAND
V DATA L
Freescale Semiconductor
START ADDR
OPCODE
—
Figure
Rev. 3.0