MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 110

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGM)
8.6.4 H & V Sync Output Control Register (HVOCR)
Data Sheet
110
HVOCR[1:0]
00
01
10
11
Register Settings
MUL[7:4]
3
5
8
9
Address:
The H&V sync output control register controls the PLL reference input
prescaler and the final free-running waveforms for the sync processor
output signals on HOUT, VOUT, DCLK, and DE pins.
(See
DCLKPH[1:0] — DCLK Output Phase Adjustment
HVOCR[1:0] — Free Running Video Mode Select Bits
Reset:
Read:
Write:
These two bits are programmed to adjust the DCLK output phase.
Each increment adds approximately 2 to 3ns delay to the DCLK output.
These two bits together with MUL[7:4] and VRS[7:4] in the PLL
programming register determine the frequencies of the internal
generated free-running signals for output to HOUT, VOUT, DE, and
DCLK pins, when the SOUT bit is set in the sync processor I/O control
register. These two bits determine the prescaler of PLL reference
clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2;
for other values, the prescaler is 3. Reset clears these bits, setting a
default horizontal frequency of 31.25kHz and a vertical frequency of
60Hz, a video mode of 640×480.
VRS[7:4]
Figure 8-6. H&V Sync Output Control Register (HVOCR)
Section 17. Sync
3
3
6
9
$003F
Bit 7
Clock Generator Module (CGM)
Frequency
31.45kHz
37.87kHz
48.37kHz
64.32kHz
= Unimplemented
HOUT
6
Processor.)
Pin Outputs
5
Frequency
59.91Hz
60.31Hz
60.31Hz
60.00Hz
VOUT
DCLKPH1 DCLKPH0
4
0
Frequency
108MHz
24MHz
40MHz
64MHz
DCLK
R
3
0
MC68HC908LD64
= Reserved
Freescale Semiconductor
2
R
SXGA 1280 × 1024
SVGA 800 × 600
XGA 1024 × 768
DE Video Mode
VGA 640 × 480
Video Modes
HVOCR1 HVOCR0
1
0
—
Rev. 3.0
Bit 0
0