MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 111
MC908LD64IFUE
Manufacturer Part Number
MC908LD64IFUE
Description
IC MCU 8BIT FOR LCD 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LD64IFUE.pdf
(362 pages)
Specifications of MC908LD64IFUE
Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
I²C, USB
Peripherals
OSD, POR, PWM
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LD
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, USB
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908LD64IFUE
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC908LD64IFUE
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8.7 Interrupts
8.8 Low-Power Modes
8.8.1 Wait Mode
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock CGMVCLK, can be selected as the
DCLK1 source by setting BCS in the PCTL. When the PLL exits lock, the
VCO clock frequency is corrupt, and appropriate precautions should be
taken. If the application is not frequency-sensitive, interrupts should be
disabled to prevent PLL interrupt service routines from impeding
software performance or from exceeding stack limitations.
Software can select CGMVCLK as the DCLK1 source even if the PLL is
not locked (LOCK = 0). Therefore, software should make sure the PLL
is locked before setting the BCS bit.
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
The WAIT instruction does not affect the CGM. Before entering WAIT
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from WAIT mode also can
deselect the PLL output without turning off the PLL.
Clock Generator Module (CGM)
Clock Generator Module (CGM)
Data Sheet
Interrupts
111
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