MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 183

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.8 I/O Registers
13.8.1 ADC Status and Control Register
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
Three I/O registers control and monitor ADC operation:
Function of the ADC status and control register is described here.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
Reset:
Read:
Write:
•
•
•
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written, or whenever the ADC
data register is read. Reset clears this bit.
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is
a read-only bit, and will always be logic 0 when read.
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status and control register is written. Reset clears the
AIEN bit.
Figure 13-3. ADC Status and Control Register (ADSCR)
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC input clock register (ADICLK)
$003B
COCO
Bit 7
Analog-to-Digital Converter (ADC)
0
= Unimplemented
AIEN
6
0
ADCO
5
0
ADCH4
4
1
ADCH3
3
1
Analog-to-Digital Converter (ADC)
ADCH2
2
1
ADCH1
1
1
I/O Registers
Data Sheet
ADCH0
Bit 0
1
183