MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 47

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LD64
Freescale Semiconductor
Addr.
$001C
$001D
$001A
$001B
$0014
$0015
$0016
$0017
$0018
$0019
DDC2 Address Register
DDC Address Register
DDC Control Register
Register Name
DDC Status Register
DDC Master Control
DDC Data Transmit
DDC Data Receive
Unimplemented
U = Unaffected
TIM Channel 1
TIM Channel 1
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 15)
Register High
Register Low
(DDC2ADR)
—
(DDCMCR)
(DDCDRR)
(DDCADR)
(DDCDTR)
(DDCCR)
(DDCSR)
Rev. 3.0
(TCH1H)
(TCH1L)
Register
Register
Register
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Read:
Read:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
X = Indeterminate
D2AD7
DAD7
DTD7
DRD7
Bit15
RXIF
Bit 7
ALIF
DEN
Bit7
0
1
0
0
0
1
0
0
D2AD6
NAKIF
DAD6
DRD6
DTD6
DIEN
Bit14
TXIF
Bit6
6
0
0
0
0
0
1
0
0
Memory Map
MATCH
D2AD5
DRD5
DAD5
DTD5
Bit13
Bit5
BB
5
0
1
0
0
0
1
0
0
Indeterminate after reset
Indeterminate after reset
= Unimplemented
D2AD4
MAST
DRD4
DAD4
DTD4
Bit12
SRW
Bit4
4
0
0
0
0
0
1
0
0
D2AD3
RXAK
DRD3
DAD3
TXAK
DTD3
MRW
Bit11
Bit3
3
0
0
0
1
1
0
0
SCLIEN
D2AD2
SCLIF
DAD2
DTD2
DRD2
Bit10
BR2
Bit2
Input/Output (I/O) Section
R
2
0
0
0
0
0
1
0
0
= Reserved
DDC1EN
D2AD1
DRD1
DAD1
TXBE
DTD1
BR1
Bit9
Bit1
1
0
0
0
1
1
0
0
Memory Map
Data Sheet
EXTAD
RXBF
DRD0
DTD0
Bit 0
BR0
Bit8
Bit0
0
0
0
0
0
1
0
0
0
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