MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 22

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

List of Figures
Data Sheet
22
Figure
8-5
8-6
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 126
9-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . 129
9-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . 129
9-14 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9-15 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 132
9-16 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 132
9-17 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9-18 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 133
9-19 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 134
9-20 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 135
9-21 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 136
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
11-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11-2 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 156
11-3 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 161
11-4 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 163
11-5 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 164
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . . 108
H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . . 110
SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .116
OSC Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
List of Figures
Title
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Page