MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 267

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.6.5 Sync Processor Control Register 1 (SPCR1)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
LVSIE — Low VSync Interrupt Enable
LVSIF — Low VSync Interrupt Flag
HPS[1:0] — HSYNC input Detection Pulse Width
Reset:
Read:
Write:
When this bit is set, the LVSIF flag is enabled to generate an interrupt
request to the CPU. When LVSIE is cleared, the LVSIF flag is
prevented from generating an interrupt request to the CPU. Reset
clears this bit.
This read-only bit is set when the value of VFR is higher than $C00
(vertical frame frequency below 40.7Hz). LVSIF generates an
interrupt request to the CPU if the LVSIE is also set. This bit is cleared
by writing a "0" to it or reset.
These two bits control the detection pulse width of HSYNC input.
Reset clears these two bits, setting a default middle frequency of
HSYNC input.
Figure 17-10. Sync Processor Control Register 1 (SPCR1)
1 = Low Vsync interrupt enabled
0 = Low Vsync interrupt disabled
1 = Vertical frequency is below 40.7Hz
0 = Vertical frequency is higher than 40.7Hz
HPS1
$0046
LVSIE
Bit 7
Table 17-7. HSYNC Polarity Detection Pulse Width
0
1
0
0
= Unimplemented
LVSIF
Sync Processor
6
0
0
HPS1
5
0
HPS0
X
0
1
HPS0
4
0
R
R
3
Polarity Detection Pulse Width
Long > 14µs and Short < 12µs
Long > 3.5µs and Short < 3µs
Long > 7µs and Short < 6µs
Sync Processor I/O Registers
= Reserved
R
2
ATPOL
Sync Processor
1
0
Data Sheet
FSHF
Bit 0
0
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