MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 24

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

List of Figures
Data Sheet
24
Figure
14-21 USB Embedded Device Endpoint 1/2 Data Registers
15-1 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 223
15-2 Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 224
15-3 Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 225
15-4 Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 226
15-5 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 228
15-6 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 230
15-7 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 231
15-8 Data Transfer Sequences for Master/Slave
16-1 DDC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 237
16-2 DDC Address Register (DDCADR). . . . . . . . . . . . . . . . . . . . . 238
16-3 DDC2 Address Register (DDC2ADR). . . . . . . . . . . . . . . . . . . 239
16-4 DDC Control Register (DDCCR). . . . . . . . . . . . . . . . . . . . . . . 240
16-5 DDC Master Control Register (DDCMCR) . . . . . . . . . . . . . . . 241
16-6 DDC Status Register (DDCSR) . . . . . . . . . . . . . . . . . . . . . . .244
16-7 DDC Data Transmit Register (DDCDTR) . . . . . . . . . . . . . . . . 246
16-8 DDC Data Receive Register (DDCDRR) . . . . . . . . . . . . . . . . 247
16-9 Data Transfer Sequences for Master/Slave
17-1 Sync Processor I/O Register Summary . . . . . . . . . . . . . . . . . 254
17-2 Sync Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . .255
17-3 Clamp Pulse Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17-4 Sync Processor Control & Status Register (SPCSR) . . . . . . . 259
17-5 Sync Processor Input/Output Control Register (SPIOCR) . . . 261
17-6 Vertical Frequency High Register . . . . . . . . . . . . . . . . . . . . . . 263
17-7 Vertical Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . 263
17-8 Hsync Frequency High Register . . . . . . . . . . . . . . . . . . . . . . . 265
17-9 Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . .265
17-10 Sync Processor Control Register 1 (SPCR1) . . . . . . . . . . . . . 267
17-11 H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . . 268
(DE1D0–DE1D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 249
List of Figures
Title
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Page