MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 53

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LD64
Freescale Semiconductor
* RSTF and USBEN are reset by a power-on reset (POR) only.
Addr.
$0050
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
USB SIE Timing Interrupt
USB HUB Downstream
USB HUB Downstream
USB HUB Downstream
USB HUB Downstream
USB SIE Timing Status
Port 1 Control Register
Port 2 Control Register
Port 3 Control Register
Port 4 Control Register
Register Name
USB HUB Interrupt
USB HUB Address
Unimplemented
Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 15)
—
(HDP1CR)
(HDP2CR)
(HDP3CR)
(HDP4CR)
Register 0
(SIETSR)
(HADDR)
Rev. 3.0
(SIETIR)
Register
Register
Register
(HIR0)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
X = Indeterminate
USBEN
PEN1
PEN2
PEN3
PEN4
SOFF
RSTF
TXDF
Bit 7
0*
0*
0
0
0
0
0
0
LOWSP1
LOWSP2
LOWSP3
LOWSP4
RSTFR
EOF2F
ADD6
RXDF
6
0
0
0
0
0
0
0
0
0
Memory Map
LOCKF
EOPF
ADD5
RST1
RST2
RST3
RST4
5
0
0
0
0
0
0
0
0
0
= Unimplemented
RESUM1
RESUM2
RESUM3
RESUM4
LOCKFR
TRANF
ADD4
4
0
0
0
0
0
0
0
0
0
0
SUSP1
SUSP2
SUSP3
SUSP4
SOFFR
SOFIE
TXDIE
ADD3
3
0
0
0
0
0
0
0
0
0
EOF2FR
EOF2IE
RXDIE
ADD2
Input/Output (I/O) Section
R
2
0
0
0
0
0
0
0
0
0
0
0
0
0
= Reserved
EOPFR
TXDFR
EOPIE
ADD1
D1+
D2+
D3+
D4+
1
X
X
X
X
0
0
0
0
0
0
Memory Map
Data Sheet
TRANFR
TRANIE
RXDFR
ADD0
Bit 0
D1–
D2–
D3–
D4–
X
X
X
X
0
0
0
0
0
0
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