MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 240

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

DDC12AB Interface
16.6.3 DDC Control Register (DDCCR)
Data Sheet
240
Address:
DEN — DDC Enable
DIEN — DDC Interrupt Enable
TXAK — Transmit Acknowledge Enable
Reset:
Read:
Write:
This bit is set to enable the DDC module. When DEN = 0, module is
disabled and all flags will restore to its power-on default states. Reset
clears this bit.
When this bit is set, the TXIF, RXIF, ALIF, and NAKIF flags are
enabled to generate an interrupt request to the CPU. When DIEN is
cleared, the these flags are prevented from generating an interrupt
request. Reset clears this bit.
This bit is set to disable the DDC from sending out an acknowledge
signal to the bus at the 9th clock bit after receiving 8 data bits. When
TXAK is cleared, an acknowledge signal will be sent at the 9th clock
bit. Reset clears this bit.
1 = DDC module enabled
0 = DDC module disabled
1 = TXIF, RXIF, ALIF, and/or NAKIF bit set will generate interrupt
0 = TXIF, RXIF, ALIF, and/or NAKIF bit set will not generate
1 = DDC does not send acknowledge signals at 9th clock bit
0 = DDC sends acknowledge signal at 9th clock bit
$0018
DEN
Bit 7
request to CPU
interrupt request to CPU
0
Figure 16-4. DDC Control Register (DDCCR)
= Unimplemented
DDC12AB Interface
DIEN
6
0
5
0
0
4
0
0
TXAK
3
0
MC68HC908LD64
SCLIEN
Freescale Semiconductor
2
0
DDC1EN
1
0
—
Rev. 3.0
Bit 0
0
0