UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 193

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(6) Operation of OVF0n flag
(7) Conflicting operations
<1> The OVF0n flag is also set to 1 in the following case.
<2> Even if the OVF0n flag is cleared before the next count clock is counted (before TM0n becomes 0001H)
Conflict between the read period of the 16-bit timer capture/compare register (CR000/CR010) and capture trigger
input (CR000/CR010 used as capture register)
Capture trigger input has priority. The data read from CR000/CR010 is undefined.
When of the following modes: the mode in which clear & start occurs on a match between TM0n and
CR00n, the mode in which clear & start occurs on a TI000 pin valid edge, or the free-running mode, is
selected
TM0n is counted up from FFFFH to 0000H.
after the occurrence of TM0n overflow, the OVF0n flag is re-set newly and clear is disabled.
Remark n = 0:
CR010 capture value
Capture read signal
TM00 count value
CR00n is set to FFFFH
n = 0, 1: PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, and 78F0386D
Count clock
Edge input
INTTM010
Count clock
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
INTTM00n
Figure 6-42. Capture Register Data Retention Timing
PD78F0372, 78F0373, 78F0382, and 78F0383
OVF0n
CR00n
TM0n
Figure 6-41. Operation Timing of OVF0n Flag
X
N
FFFEH
FFFFH
User’s Manual U17504EJ2V0UD
N + 1
FFFFH
Capture
N + 2
0000H
0001H
N + 2
M
Capture, but
read value is
not guaranteed
M + 1
M + 1
M + 2
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