UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 290

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

288
(d) Reception
R
X
D0 (input)
Reception is enabled and the R
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the R
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
R
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception.
INTSR0 occurs upon completion of reception and in case of a reception error.
Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status
INTSR0
X
RXB0
D0 pin input is sampled again (
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
is ignored.
Start
Figure 13-9. Reception Completion Interrupt Request Timing
D0
CHAPTER 13 SERIAL INTERFACE UART0
D1
X
D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
in Figure 13-9). If the R
User’s Manual U17504EJ2V0UD
D2
D3
D4
D5
X
D0 pin is low level at this time, it is recognized
D6
D7
Parity
Stop
X
D0 pin input is