UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 606

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

31.2 Peripheral Hardware That Generates Wait
clocks.
Caution When the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped,
Remark The clock is the CPU clock (f
604
Serial interface
UART0
Serial interface
UART6
Serial interface
IIC0
A/D converter
Table 31-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait
Peripheral
Hardware
do not access the registers listed above using an access method in which a wait request is issued.
Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks
ASIS0
ASIS6
IICS0
ADM
ADS
ADPC
ADCR
The above number of clocks is when the same source clock is selected for f
clocks can be calculated by the following expression and under the following conditions.
<Calculating number of wait clocks>
<Conditions for maximum/minimum number of wait clocks>
Number of wait clocks = {(1/f
Maximum number of times: Maximum speed of CPU (f
Minimum number of times: Minimum speed of CPU (f
* Fraction is truncated if the number of wait clocks
f
f
f
f
AD
CPU
PRS
XP
:
:
: CPU clock frequency
: Peripheral hardware clock frequency
Register
A/D conversion clock frequency (f
Main system clock frequency
CPU
CHAPTER 31 CAUTIONS FOR WAIT
).
Read
Read
Read
Write
Write
Write
Read
User’s Manual U17504EJ2V0UD
AD
)
2/(1/f
Access
CPU
)} + 1
PRS
/2 to f
PRS
SUB
0.5 and rounded up if the number of wait clocks > 0.5.
/12)
XP
/2), highest speed of A/D conversion clock (f
), lowest speed of A/D conversion clock (f
1 clock (fixed)
1 clock (fixed)
1 clock (fixed)
1 to 5 clocks (when f
1 to 7 clocks (when f
1 to 9 clocks (when f
2 to 13 clocks (when f
2 to 17 clocks (when f
2 to 25 clocks (when f
Number of Wait Clocks
CPU
and f
AD
AD
AD
AD
AD
AD
= f
= f
= f
= f
= f
= f
PRS
PRS
PRS
PRS
PRS
PRS
PRS
. The number of wait
/2 is selected)
/3 is selected)
/4 is selected)
/6 is selected)
/8 is selected)
/12 is selected)
PRS
PRS
/12)
/2)