UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 359

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

ACKE0
Condition for clearing (ACKE0 = 0)
Condition for clearing (SPIE0 = 0)
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling
edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the
falling edge of the ninth clock after an acknowledge signal (ACK) is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
Notes 1. This flag’s signal is invalid when IICE0 = 0.
WTIM0
SPIE0
Cleared by instruction
Reset
Cleared by instruction
Reset
Cleared by instruction
Reset
0
1
0
1
0
1
Notes 1, 2
Note 1
Note 1
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledge signal is generated
regardless of the set value.
Disable
Enable
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However, ACK is
invalid during address transfers and other than in expansion mode.
Figure 16-5. Format of IIC Control Register 0 (IICC0) (2/4)
Enable/disable generation of interrupt request when stop condition is detected
CHAPTER 16 SERIAL INTERFACE IIC0
Control of wait and interrupt request generation
User’s Manual U17504EJ2V0UD
Acknowledgment control
Condition for setting (SPIE0 = 1)
Condition for setting (WTIM0 = 1)
Condition for setting (ACKE0 = 1)
Set by instruction
Set by instruction
Set by instruction
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