UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 391

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It
is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual
data communication is performed by the main processing.
Therefore, data communication processing is performed by preparing the following three flags and passing
them to the main processing instead of INTIIC0.
<1> Communication mode flag
<2> Ready flag
<3> Communication direction flag
This flag indicates the following two communication statuses.
This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt
for ordinary data communication.
processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag
is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted
without the flag being cleared (an address match is interpreted as a request for the next data).
This flag indicates the direction of communication. Its value is the same as TRC0.
Clear mode:
Communication mode: Status in which data communication is performed (from valid address detection
IIC0
INTIIC0
Setting
Status in which data communication is not performed
to stop condition detection, no detection of ACK from master, address
mismatch)
CHAPTER 16 SERIAL INTERFACE IIC0
User’s Manual U17504EJ2V0UD
This flag is set by interrupt servicing and cleared by the main
Interrupt servicing
Setting
Data
Flag
Main processing
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