UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 515

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Notes 1.
Serial interface IIC0
LCD controller/driver
Multiplier/divider
Key interrupt
Reset function
Low-voltage detector
Interrupt
2.
3.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, 78F0386D only.
Register
RESF
LVIM
LVIS
Note 2
Table 22-2. Hardware Statuses After Reset Acknowledgment (3/3)
Reset Source
WDTRF bit
LVIRF bit
Shift register 0 (IIC0)
Control register 0 (IICC0)
Slave address register 0 (SVA0)
Clock selection register 0 (IICCL0)
Function expansion register 0 (IICX0)
Status register 0 (IICS0)
Flag register 0 (IICF0)
LCD mode setting register (LCDMD)
LCD display mode register (LCDM)
LCD clock control register (LCDC)
LCD voltage boost control register 0 (VLCG0)
Remainder data register 0 (SDR0)
Multiplication/division data register A0 (MDA0H, MDA0L)
Multiplication/division data register B0 (MDB0)
Multiplier/divider control register 0 (DMUC0)
Key return mode register (KRM)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Cleared (0)
Cleared (00H)
RESET Input
CHAPTER 22 RESET FUNCTION
Hardware
User’s Manual U17504EJ2V0UD
Cleared (0)
Cleared (00H)
Reset by POC
Set (1)
Held
Cleared (00H)
Reset by WDT
Held
Set (1)
Held
Reset by LVI
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
Acknowledgment
Status After Reset
Note 3
Note 3
Note 3
Note 1
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