UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 577

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Call/return
Stack
manipulate
Unconditional
branch
Conditional
branch
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
!addr16
!addr11
[addr5]
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Operands
CHAPTER 28 INSTRUCTION SET
User’s Manual U17504EJ2V0UD
Bytes
3
2
1
1
1
1
1
1
1
1
1
4
2
2
3
2
2
2
2
2
2
Note 1
7
5
6
6
6
6
6
2
4
2
4
6
6
8
6
6
6
6
Clocks
Note 2
10
8
8
(SP
PC
(SP
PC
SP
(SP
PC
PC
SP
(SP
(SP
PC
PC
SP
PC
PSW
PC
PSW
(SP
(SP
SP
PSW
rp
SP
SP
SP
AX
PC
PC
PCH
PC
PC
PC
PC
H
15
H
L
L
H
H
H
1)
1)
11
1)
1)
3)
1)
1)
SP
SP
SP + 2
SP
(SP + 1), rp
SP + 2
word
AX
SP
addr16, SP
addr16
PC + 2 + jdisp8
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
(00000000, addr5),
(003EH), SP
(00000000, addr5 + 1),
(SP + 1), PC
(SP + 1), PC
(SP + 1), PC
A, PC
(SP + 2), SP
(SP + 2), SP
(SP), SP
00001, PC
(PC + 3)
(PC + 2)
(PC + 1)
PSW, (SP
(PC + 1)
PSW, SP
rp
2
2
2
CPU
H
L
, (SP
) selected by the processor clock
Operation
L
X
H
H
H
L
L
L
L
SP + 1
, PC
, (SP
, (SP
, (SP
SP
10
2)
(SP),
SP
2)
(SP),
(SP),
(SP),
SP
SP + 3
SP + 3
0
H
2
rp
2)
2)
2)
3, IE
addr11,
L
(PC + 1)
(003FH),
1
,
(PC + 3)
(PC + 2)
(PC + 1)
0
H
,
L
L
L
,
,
,
R R R
R R R
R R R
Z AC CY
Flag
575