UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 194

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(8) Timer operation
(9) Capture operation
(10) Compare operation
(11) Edge detection
192
<1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare
<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins
<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
<1> If the TI000 pin valid edge is specified as the count clock, a capture operation by the capture register
<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than
<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input
A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger has
been input.
<1> If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising
<2> The sampling clock used to remove noise differs when the TI000 pin valid edge is used as the count clock
register 010 (CR010).
are not acknowledged.
clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between
the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not
occur.
specified as the trigger for the TI000 pin is not possible.
the count clock selected by prescaler mode register 00 (PRM00).
(INTTM000/INTTM010), however, is generated at the rise of the next count clock.
and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter
00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful
therefore when pulling up the TI000 or TI010 pin. However, the rising edge is not detected at restart after
the operation has been stopped once.
and when it is used as a capture trigger. In the former case, the count clock is f
the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is started only
after a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17504EJ2V0UD
PRS
, and in the latter case