UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 505

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
(2) STOP mode release
High-speed system
clock (X1 oscillation)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Note When AMPH = 1
The STOP mode can be released by the following two sources.
2. Even if “internal low-speed oscillator can be stopped by software” is selected by the option
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
4. If the STOP instruction is executed with AMPH set to 1 when the internal high-speed oscillation
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillator’s oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the next execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
clock or external main system clock is used as the CPU clock, the internal high-speed
oscillation clock or external main system clock is supplied to the CPU 5 s (MIN.) after the STOP
mode has been released.
STOP mode
STOP mode release
Figure 21-5. Operation Timing When STOP Mode Is Released
Wait for oscillation
5 s (TYP.)
(oscillation stabilization time set by OSTS)
stabilization
accuracy
CHAPTER 21 STANDBY FUNCTION
Note
HALT status
User’s Manual U17504EJ2V0UD
Internal high-speed
oscillation clock
Automatic selection
Clock switched
by software
High-speed system clock
High-speed system clock
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